Professional resume

Mark Eason - Digital Engineer

Hollister, CA | 1.831.207.3228 | preprius@gmail.com

Develop Innovative Diagnostic Solutions, Streamline Testing Processes, and Enhance Design for Test in Mixed Signal ASIC designs.

Specialize in Design for Test (DFT) for mixed-signal ASICs, ensuring testability and validation throughout development. Adapt seamlessly to new software and testing environments to enhance precision. Emulate all components, run test benches before full integration (hardware in the loop), and identify issues before final production. Leverage diverse tools and methodologies to optimize functionality, refine system performance, and overcome complex design challenges. Support product development through hands-on testing, iterative improvements, and collaboration across engineering teams, ensuring seamless integration and robust validation.

Core Competencies

  • ASIC Design
  • Embedded Hardware and Software
  • Programming and Special Automation
  • System-level interfaces
  • Lab and System Integration
  • Design for Test
  • Documentation

Technical Skills

  • Verilog
  • C
  • Python
  • Simulation of Verilog mix signal, and circuits like LTC spice
  • Board layout tools (many)

Professional Experience

RENESAS ELECTRONICS (formerly iWatt | Dialog | Renesas), San Jose, CA - 2011 to 2025

Digital Engineer

  • Developed testability module for mixed-signal ASICs, enabling efficient validation and debugging.
  • Wrote RTL and stimulus for digital and AMS environments, ensuring accurate simulation and functional verification.
  • Emulated analog blocks and ran test benches before analog design was ready, identifying early design issues and streamlining integration.
  • Found bugs in functional blocks pre tapeout.
  • Fixed ECO's (post tapeout) and provided RTL and netlist changes.
  • Created chip module to provide post silicon Diagnostic port. Over 100 signals possible during normal operation. Designed lab control unit to select internal signals using Raspberry PI.
    • Challenges:
    • Faced challenges with projects that had only 5 pins, which led to difficulties in entering test mode, getting address and data in and out, and obtaining digital block scan control signals to provide digital block coverage.
    • Got analog team to think about coverage, and bench (analog) programmers group to accept variations.
  • Created designs that are in over 3B units.
  • Wrote python code to control lab bench equipment for automated functional (power supply) testing and to check byte error rate in new communication protocol.

EXCLARA INC, Santa Clara, CA - 2006 to 2011

Startup company for LED drivers. Digital ASIC Engineer

  • Architected digital cores for mixed signal LED controllers including testability (DFT).
  • Implemented Verilog code and simulated entire chip, including analog blocks, which emulated target circuits for LED applications and proved that system RTL works.
  • Designed test board to emulate analog blocks, downloaded and tested design, and laid out circuit boards to emulate analog blocks for testing digital RTL (download and test).
  • Performed synthesis, place and route for digital block using Magma Talus.
  • Created in-house test board for ASIC testing, helped with PIC controller code, and conducted LabVIEW testing.
  • Designed demo real street lights (LED) units for marketing / sales group and acquired real street lights from PGE for lab demos.
  • Closed up Exclara and went back to iWatt because the market was not ready for LED drivers yet, ran out of VC capital.

IWATT INC, Campbell, CA - 2001 to 2006

Startup for flyback controllers. Employee #9. Digital ASIC Developer Engineer

  • Created digital core for mixed signal power supply controllers, using Xilinx boards and ISE tools to download and test RTL into power supply emulation boards.
  • Invented digital error feedback mechanism for primary side feedback, working with analog to design new digital sensor without A/D module.
  • Added test function into core to give ability into design for trimming, tested analog blocks for ATE, and re-used digital functional blocks for DFT purposes, which saved space and provided better digital block test coverage.
  • Worked with analog and simulated design, creating digital blocks inside RTL to emulate analog blocks, which also emulated full chip.
  • Learned synthesis tools and place and route tools for my first IC design, went through all steps of digital layout tools, working with analog layout guy to get pin files and layout files to be used in digital layout tools.
  • Designed the first sellable chip, which was a 5-pin part with no scan, and achieved 80% digital block coverage despite having no die area for scan mode.
  • Worked with analog team and IC layout engineer to perform digital ECO, which ensured successful integration of digital and analog components.

Additional Relevant Experience

HIFN INC, Los Gatos, CA - 1999 to 2001

Security Encryption. Hardware Embedded Engineer (pre-post Test ASIC)

  • Developed in-house test emulation platform to validate ASIC code for security encryption.
  • Identified and reported bugs in IP and designer code, to ensure reliability and performance.
  • Tested interfaces including MPC860, MPC8260, PCI, and synchronous buses for network processors.
  • Designed post-silicon test boards to generate "Shmoo" plots, using software-controlled oscillators, voltage regulation, and Peltier-based temperature control.

DATUM INC., San Jose, CA - 1997 to 1999

Bancomm Timing Division. Hardware Embedded Engineer

  • Designed control boards for precise timing instruments and utilized Xilinx, 68CH11, MPC860, 68360, VCOs, and GPS receivers.
  • Engineered systems to achieve a timing drift of less than 5ns per week.
  • Conducted validation using Rubidium and Cesium clocks to ensure accuracy and stability.

INTEGRATED SYSTEMS INC., Santa Clara, CA - 1995 to 1997

Applied Solution Division. Hardware Engineer

  • Developed specialized hardware for control system applications and designed mechanical enclosures to house custom boards.
  • Utilized Xilinx and Lattice PLDs, dual-port RAMs, and interfaced with PC104 and TI DSP ports.
  • Designed boards as part of custom controllers for military (hardware in the loop), semiconductor industry, and Iridium satellite systems.
  • Collaborated with the software team to ensure seamless integration into final deliverables.

WYLE LABS, Edwards Air Force Base, CA - 1991 to 1995

location: "Rocket Site Road" Flight Hardware Embedded Engineer

  • Designed 6 VME boards for satellite sensor integration and developed software for testing and validation.
  • Conducted environmental testing, including vibration and thermal assessments (shake and bake), to ensure flight readiness.
  • Supported successful deployment of 3 satellites within 3 years (MSTI satellites).

NORTHRUP CORPORATION, B2 Division, Pico Rivera, CA - 1985 to 1990

Digital Engineer (Digital Development Lab)

  • Designed test and evaluation circuits for B2 project, to support both in-flight and ground operations.
  • Devices used: Altera EPLD, Xilinx, 8751 uC.
  • Protocols: proprietary Northrup Data Systems (NDS) stack. 1553 bus.
  • Software: Assembly and C.

Mechanical CAD engineer (1.5 yrs)

  • Developed and documented installation of in-flight electronic systems, including instrumentation and cooling solutions for test environments.
  • Developed air duct designs to optimize thermal management in electronic racks for the Flying Test Bed.
  • Created detailed documentation for instrumentation racks in the dynamic wing laboratory.
  • Specialized in electronics throughout schooling, with no emphasis on mechanical studies. Applied CAD drawing experience from Rockwell to transition to Northrop.
  • Discovered digital lab and initiated transfer request, securing the move.

ROCKWELL SPACE TRANSPORTATION SYSTEMS, Downey, CA - 1980 to 1985

Space Shuttle Standard Component Engineer

  • Assisted in adding mechanical components into 3D CAD.

Education

Bachelor of Science (BS), Electronics, DeVry Institute Technology, Phoenix, AZ